1. Field of the Invention
The present invention relates to a microcomputer which comprises a built-in serial input-output circuit which outputs data in converting parallel data into serial data and converts input serial data into parallel data.
2. Description of the Prior Art
FIG. 5 is a block diagram showing the internal configuration of a serial input-output circuit (SIO) which realizes synchronous data transfer which is shown in a user's manual for Mitsubishi microcomputer M37477/M37478 group (issued by Mitsubishi Electric Corporation in March, 1994). In the figure, there are shown a clock signal control portion 51 which forms a data transfer clock signal using a clock signal given by an Xin or SCLK, a receiving shift register 52 which shifts a serial receiving signal input from an R.times.D terminal, a receiving buffer register 53 which inputs the data in the receiving shift register 52 when the receiving shift register 52 is full of data, a transmitting buffer register 54 in which transmitting data are set, a transmitting shift register 55 which inputs the transmitting data in the transmitting buffer register 54 and serializes the transmitting data and outputs the data to a T.times.D terminal, a switch 56 which decides the generating point of time of an interrupt signal to be given to the CPU whether it is the point of time when the data in the transmitting buffer register 54 are transferred to the transmitting shift register 55 or it is the point of time when the data in the transmitting shift register 55 are completely output, and a data bus 110. Either a clock signal generated in the microcomputer or a clock signal input from an external circuit can be used as a clock signal from the Xin.
FIG. 6 is a block diagram showing the internal configuration of a one-chip microcomputer having a built-in SIO. In the figure, reference numeral 101 represents a CPU which executes predetermined operation or control according to a program stored in a ROM 102; 103, a RAM for storing data; 104, a timer for measuring necessary period of time, etc.; 105, an input-output port for performing interchange of data with an external circuit; 106, a D-A converter which outputs data to the external circuit in converting digital values to analog values; 107, an A-D converter which outputs data to the external circuit in converting analog values to digital values; 108, the SIO shown in FIG. 5; and 109, a clock signal generator for generating a clock signal. In the microcomputer, the input-output line for the D-A converter 106, the A-D converter 107 and the SIO 108 is used in common with the input-output line for the IO port 105.
Next, the operation will be explained. In the case of transmission, the CPU 101 performs a predetermined setting for an SIO control register (not shown) and after that, writes the data to be transmitted in the transmitting buffer register 54. The contents of the transmitting buffer register 54 are transferred to the transmitting shift register 55. In the case where the switch 56 is so set that an interrupt signal TI is generated when the data in the transmitting buffer register 54 is transferred to the transmitting shift register 55, an interrupt signal is generated. When there are data to be transmitted in the next step, the CPU 101 writes the data to the transmitting buffer register 54. The written data are transferred to the transmitting shift register 55 when all data in the transmitting shift register 55 are output.
The transmitting shift register 55 shifts data according to the clock signal from the clock control portion 51. The bits squeezed out of the transmitting shift register 55 are output from the T.times.D terminal. In the case where the switch 56 is so set that an interrupt signal TI is generated when all data in the transmitting shift register 55 are output, the interrupt signal TI is generated when all bits in the transmitting shift register 55 are output from the T.times.D terminal.
In a receiving period, the receiving shift register 52 takes in the data input through the R.times.D terminal in accordance with the clock signal from the clock signal control portion 51 and shifts the content bit by bit. When the data corresponding to the bit length of the receiving shift register 52 is input, the data in the receiving shift register 52 are transferred to the receiving buffer register 53. At the same time, an interrupt signal RI is generated. An RBF (receiving buffer full) flag in the SIO control register is made ON. The CPU 101, in correspondence to the interrupt signal, or detecting the ON of the RBF flag, takes in data from the receiving buffer register 53.
FIG. 7 is a block diagram showing the internal configuration of the SIO for realizing asynchronous data transfer which is described in the above user's manual. In the figure, there are shown a ST detector 57 for detecting a start bit, and an ST/SP/PA generator 58 for generating a start bit, a stop bit and a parity bit.
Next, the operation will be explained. The operation in a transmitting period is about the same as that shown in FIG. 5. However in this case, preceding the output of a first bit in the transmitting shift register 55, the ST/SP/PA generator 58 outputs a start bit to the T.times.D terminal. After the output of an end bit in the transmitting shift register 55, a stop bit is output to the T.times.D terminal by the ST/SP/PA generator 58. In the case where a parity permission flag in the SIO control register is ON, the ST/SP/PA generator 58 forms a parity bit and outputs it to the T.times.D terminal.
The operation in a receiving period is about the same as that shown in FIG. 5. However in this case, when a start bit is detected by the ST detector 57, the following serial data are supplied to the receiving shift register 52. When a stop bit is detected by the ST detector 57, the data in the receiving shift register 52 are transferred to the receiving buffer register 53.
In the M37477/M37478, an SIO realizes either synchronous data transfer or asynchronous data transfer corresponding to the setting of a predetermined bit in the SIO control register.
It is considered to constitute a LAN with microcomputers utilizing the SIO function of the microcomputers. There is an ISO/DIS 11519-3 (J1850) standard for example, as a LAN standard which can be applied to such a LAN. The J1850 standard is a LAN standard of a bus type of a so called multimaster system. In the J1850 standard, there is a period of time in which respective terminal stations output priority codes following the start bit period of time. When a certain terminal station, a microcomputer in this case, outputs a start bit to a transmission line, other microcomputers which desire to output data output start bits to the transmission line simultaneously. Following the above, the microcomputers which desire to output data output priority codes to the transmission line. The data such as start bits or priority codes are PWM pulses as shown in FIG. 8. The priority code sent out by a microcomputer having the highest priority remains in the transmission line.
Therefore, the data and the priority code are compared with each other and when they coincide, a transmitting right is allotted. The process of obtaining the transmission right as described in the above is called arbitration. The comparison between the data and the priority code on the transmission line is called an arbitration judgment. The example shown in FIG. 8 shows a state wherein the priority code sent out by a microcomputer on a B side coincides with the data on the transmission line and the microcomputer on the B side continues transmission. Since a fourth bit in the priority code sent out by a microcomputer on an A side does not coincide with that in the data on the transmission line, the transmission of data is stopped, and since a second bit in the priority code sent out by a microcomputer on a C side does not coincide with that in the data on the transmission line, the transmission of data is stopped.
In order to communicate in a LAN which requires the above-mentioned collision detection, it is good to add LAN control circuits 120a, 120b and 120c having a collision detection function respectively to microcomputers 100a, 100b and 100c, respectively, as shown in FIG. 9. Drivers 130a, 130b and 130c are provided between a transmission line 200 and the LAN control circuits 120a, 120b and 120c. With the above-mentioned configuration, a LAN communication can be realized; however, since the LAN control circuits have to be added, the cost of the system is increased.
In contrast to it, as shown in FIG. 10, a system can be considered in which the LAN control circuits 120a, 120b and 120c are eliminated, the input-output of data to the transmission line 200 is controlled by the SIO in the microcomputers 100a, 100b and 100c, and collision detection is performed with software. In such a system, the coincidence or discordance between the groups of data has to be judged by the bit in introducing the data at the T.times.D terminal and the data at the R.times.D terminal by some method or other into the CPU 101 by the bit. Taking example by the arbitration of J1850 shown in FIG. 8, the software of a microcomputer 100c on the C side has to detect discordance between groups of data before the completion of a period of a second bit of a priority code. Otherwise the microcomputer 100c on the C side sends out a priority code in a third bit to the transmission line 200. In the result, the data sent out by the microcomputer 100c on the C side are left on the transmission line 200 (refer to FIG. 8D), and the microcomputer on the A side and the microcomputer on the B side judge that their own priority codes do not coincide with the data on the transmission line 200 and both stop their transmission of data.
Since a microcomputer having a built-in serial input-output circuit is constituted as described in the above, when the transmission speed of the transmission line 200 is raised, the waking up period of the software for performing the detection of collision has to be shortened corresponding to it. However, there is a limit in the processing speed of software, therefore, there remains a problem that the transfer speed of data in a LAN is difficult to be upgraded. A prior art for collision detection, though it is not a built-in technology in a microcomputer, is shown in Japanese Patent Laid-Open No. Hei 5-233538.